1. Field of the Invention
The invention relates in general to a semiconductor element and a process for producing the same, and more particularly to improvements in an interfacial property between a semiconductor layer and an insulating layer and a leak current along with a thin film transistor and a process for producing the same.
2. Description of the Prior Art
Generally, a thin film transistor (hereinafter "TFT") for operating a liquid crystal display (hereinafter "LCD") employs amorphous silicon or polysilicon for an active semiconductor layer. Since the mobility of electrons in the amorphous silicon is very low, it is not suitable for operating an LCD which requires a high density and high definition. On the other hand, the mobility in the polysilicon is high, so that it is used as an active semiconductor in a TFT for operating an LCD.
Recently, high temperature treatment has been applied to the production of TFT to form an oxide film as well as to effect a change of the amorphous silicon into polysilicon. However, the high temperature treatment causes a leak current to increase in a manufactured TFT. In addition, there is insufficient carrier mobility in the conventional TFT.
Hereinafter, these problems will be briefly discussed for better understanding of the background of the invention. For this, a conventional process for producing a TFT and the structure of the TFT will be explained referring to FIG. 1.
As shown in step A, the conventional TFT is formed of a clean, well-dried insulating substrate 1 such as quartz. A semiconductor layer 2 of either polysilicon or amorphous silicon is deposited on the insulating substrate 1 at a thickness of approximately 1,500 .ANG.. Thereafter, it is selectively etched by photoetching to pattern an active layer in a desired shape. Thermal oxidation process is applied to the surface of the patterned semiconductor layer to form a gate oxide film 3 which covers the semiconductor layer 2. This thermal oxidation process is conducted at a high temperature to grow the gate oxide film 3 at a thickness of approximately 500 to 1,000 .ANG.. At this time, in the case that the amorphous silicon is employed for the semiconductor 2, it is crystallized through the thermal treatment to be ultimately transformed into polycrystalline.
Next, in step B, polysilicon doped with impurities is grown on the gate oxide film 3 at a thickness of approximately 2,000 to 5,000 .ANG., using a chemical vapor deposition method. Then, photoetching is undertaken to carry out removing an unnecessary part of the doped polysilicon to form a gate 4.
Subsequently, in step C, utilizing the gate 4 as a mask, a desired type impurity is ion-implanted at the dose of, for example, 1.times.10.sup.13 to 1.times.10.sup.18 /cm.sup.2 to form a self-aligned source region 5-1 and drain region 5-2 as shown in the figure.
Step D is undertaken to form contact holes. For this, an oxide film (SiO.sub.2) 6 which acts as an insulating film is initially formed on the whole surfaces of the substrate and the previously formed parts according to the regular method including CVD and is then subjected to the treatment of selective photoetching to expose a part of the gate 4 and the source region 5-1 and drain region 5-2.
Lastly, in step E, metal material such as aluminum, molybdenum/aluminum (Mo/Al) and the like is entirely deposited by sputtering. Thereafter, photoetching is carried out to form an electrode 7 which is so patterned that the metal is left over only the exposed parts of the source region 5-1, drain region 5-2 and the gate 4.
As described before, a conventional TFT comprises a substrate 1, a source region 5-1 and drain region 5-2 formed on the predetermined surface of the substrate 1, a channel region (a semiconductor layer 2 between the source region and the drain region), a gate oxide film 3 and a gate 4 formed on the channel region, an electrode 7 formed on the source region 5-1 and drain region 5-2 and on the gate 4, and an insulating film 6 formed on the entire surface except the electrode 7.
Applying electric power to the gate electrode 7 formed on the gate 4 in the conventional TFT, electrons or holes come to gather, so as to form a channel. As a result, the source region 5-1 is electrically conducted to the drain region 5-2, so that the conventional TFT comes to play the role of an operating switch for an LCD.
However, if the electrode 7 is provided with a negative voltage, most of the voltage generated between the source region 5-1 and the drain region 5-2 is concentrated on the vicinity of the drain region 5-1 and the channel. As a result, there occurs a charge pair due to charge collision and a tunneling effect in the charge trap level, so that a leak current is increased in the TFT. Consequently, the conventional TFT performs the function of an electrical switch for an LCD unsatisfactory and the conventional process for producing TFT attenuates the desirable characteristics of a semiconductor element.